(1) Field of the Invention
The invention relates to the manufacture of highly dense integrated circuits and more particularly to the formation of polycide-to-polycrystalline silicon capacitors and field effect transistor (FET) devices within the integrated circuit.
(2) Description of the Related Art
In recent years there continues to be dramatic density increases in the integrated circuit technology. The minimum feature size of lithography has been reduced to one micrometer and below. In the fabrication of precision capacitors in conjunction with FET devices on the same chip at these reduced dimensions, it is increasingly difficult to maintain such parameters as low voltage and temperature coefficients and low leakage current.
Workers in the field have described the formation of capacitors using two layers of polysilicon. McDonald in U.S. Pat. No. 5,037,772 describes a method for fabricating a polysilicon-to-polysilicon capacitor on the same chip as CMOS and BiCMOS devices. A first polysilicon layer is deposited and ion-implanted with arsenic. A silicon oxide/silicon nitride dielectric layer is then formed and patterned to the capacitor dimensions. A second polysilicon layer is deposited. An anisotropic etch is then performed, with the dielectric layer acting as a mask to protect the first polysilicon layer.
In European Patent Application 0 183 623, Krishner also describes a process for producing a precision polysilicon-to-polysilicon capacitor in conjunction with MOS devices on the same chip. However, it is noted that the deposition of silicon nitride as part of the dielectric layer causes uniformity problems, due to the difficulty of depositing a uniformly thick layer of the silicon nitride. Thus in this invention a single layer of thermally grown silicon dioxide is used as the capacitor dielectric. The oxidation process includes an annealing step. The dielectric layer is grown from a first polysilicon layer that has been ion-implanted with phosphorus or arsenic. A low energy implant is described which allows for precise control of the subsequent dielectric thickness. However, neither this approach nor that in U.S. Pat. No. 5,037,772 directly addresses the problems of non-linearity and instability of the capacitor voltage coefficient, high voltage and temperature coefficients, high leakage current, and unstable oxide capacitance, as feature sizes are reduced to one micrometer and less.
In addition, the use of polycide gates and capacitors, polycide being a combination of layers of polysilicon and a refractory metal silicide, is becoming very important as the industry moves to smaller device geometries. As these geometries become smaller, polysilicon becomes less satisfactory due to its high resistivity and the subsequent affect on RC time delays and IR voltage drops. The use of a combination of a top-layer refractory metal silicides with polysilicon, to form a polycide, has proven suitable because of its lower resistivity.
Polycide has typically been used in the prior art in precision capacitors in the formation of the bottom capacitor plate. The rest of the capacitor is formed by adding a dielectric and a polysilicon top plate. However, as feature sizes are reduced to one micrometer or less, this structure has the problems of non-linearity and instability of the capacitor voltage coefficient, high voltage and temperature coefficients, and unstable oxide capacitance.
A method of forming a polycide-to-polysilicon capacitor and CMOS integrated circuit to overcome these problems is described in the Related Patent Application, Ser. No. 08/102,977. A heavy ion-implant of the polycide bottom plate of the capacitor improves many of the capacitor characteristics noted above. However, the source/drain regions of the transistor are formed prior to doping of the polysilicon top plate of the capacitor. This can lead to a short-channel effect in the P-channel of the CMOS device, due to the high temperature drive-in during the polysilicon top-plate doping.